Thèse Conception de Circuit Ferroélectrique pour la Logique Ternaire H/F - Doctorat.Gouv.Fr

Établissement : Ecole Centrale de Lyon École doctorale : EEA - Electronique, Electrotechnique, Automatique de Lyon Laboratoire de recherche : INL - Institut des Nanotechnologies de Lyon Direction de la thèse : Alberto BOSIO ORCID 0000000161167339 Début de la thèse : 2026-10-01 Date limite de candidature : 2026-08-31T23:59:59 Energy efficiency has become a critical challenge in modern computing, from embedded IoT devices to high-performance supercomputers. Conventional CMOS-based architectures are reaching fundamental limits, including the end of Dennard scaling, rising static power dissipation, and the memory wall - data transfers between processor and memory alone account for 70 to 90% of a system's total energy budget. In-Memory Computing (IMC) is emerging as a compelling solution by embedding computation directly within memory arrays, thereby eliminating costly data movements. In this context, ferroelectric field-effect transistors (FeFETs) stand out as particularly attractive devices: they are compatible with standard CMOS fabrication processes, inherently non-volatile, and enable reconfigurable logic gates in which one operand is persistently encoded in the ferroelectric gate stack - a concept already demonstrated at INL.
This PhD thesis is carried out within the ANR eCAT project (Enabling Computer Architecture for Tomorrow), a 2025 Franco-German PRCI collaboration involving INL, Inria Rennes, Heidelberg University, and TU Dresden. The project targets a complete heterogeneous architecture ecosystem combining RISC-V processors, FeFET-based IMC units, Near-Memory Computing (NMC), and Approximate Computing (AxC). INL leads the circuit design and device characterization workpackages.The central scientific contribution of this PhD is the exploration of ternary logic implemented through ferroelectric devices. Unlike conventional binary logic, ferroelectric materials can be programmed into stable intermediate polarization states, enabling a natural three-valued logic (0, 1, 2) within a single device. This property opens new avenues for higher integration density, reduced interconnect complexity, and greater logical expressiveness per device.The thesis unfolds in two main phases. In the first phase, the candidate will investigate the programming conditions required to reliably achieve and maintain stable intermediate ferroelectric polarization states, then design and characterize a library of elementary ternary logic gates - including ternary inverters, MIN/MAX gates, and comparators - evaluated in terms of delay, energy consumption, and endurance, using industrial EDA tools such as Cadence Virtuoso/Spectre and Synopsys. In the second phase, the work scales up to ternary arithmetic operators (adders, multipliers) targeting eCAT application workloads, with a particular focus on convolutional neural networks. Approximate computing will also be explored through deliberate modulation of the ferroelectric programming scheme, trading off precision for further energy gains. The resulting circuit models will be abstracted at multiple levels of representation and integrated into the project's system-level simulator to quantify real-world improvements in energy efficiency, computational precision, and throughput.The ideal candidate holds a Master's degree in microelectronics or a related field, with solid expertise in digital circuit design flows, semiconductor device physics, and hardware description languages (Verilog-A, VHDL, or Verilog). Familiarity with non-volatile memory technologies or ferroelectric materials is a strong asset. The position requires scientific rigor, autonomy, and the ability to collaborate within an international research consortium. Fluency in scientific English is mandatory.The PhD will be hosted at INL (UMR CNRS 5270), a multidisciplinary nanotechnology research unit affiliated with CNRS, École Centrale de Lyon, INSA Lyon, Université Lyon 1, and CPE Lyon, gathering approximately 200 researchers across two campuses in the Lyon area. Energy efficiency in computing systems is one of the major challenges facing the microelectronics industry today, from IoT devices to supercomputers. Conventional computing architectures based on CMOS technology are now facing fundamental limitations: the end of technological scaling, increasing static power consumption, and the 'memory wall' - the latter accounting for 70 to 90% of the total energy consumed by a computing system.To address these challenges, In-Memory Computing (IMC) is emerging as a promising paradigm by integrating computation directly within memory arrays, drastically reducing data transfers. In this context, ferroelectric field-effect transistors (FeFETs) are strong candidates: compatible with standard CMOS processes, non-volatile, and low-power, they enable the design of reconfigurable logic gates where one operand is permanently stored in the ferroelectric gate - an approach already demonstrated at INL.The ANR eCAT project (Enabling Computer Architecture for Tomorrow, 2025 Franco-German PRCI) brings together INL, Inria Rennes, Heidelberg University, and TU Dresden. Its goal is to build a complete ecosystem for exploring heterogeneous architectures combining RISC-V processors, FeFET-based IMC units, Near-Memory Computing (NMC), and Approximate Computing (AxC). INL leads the tasks dedicated to the characterization and design of FeFET circuits, from device to system level.This PhD thesis explores an original approach: leveraging ternary logic, made possible by the capability of ferroelectric devices to exhibit stable intermediate polarization states. This opens the door to higher integration density and logical expressiveness compared to conventional binary logic. The primary goal of this PhD is to design, model, and characterize ternary logic circuits based on ferroelectric devices (FeFET/FeCap), with a view to their integration into In-Memory Computing (IMC) units within the eCAT project's target heterogeneous architecture.Using compact ferroelectric capacitor models available at INL, the PhD candidate will:- Investigate programming conditions to achieve stable intermediate polarization states.- Design a library of elementary ternary logic gates (ternary inverter, MIN/MAX gates, comparators, etc.), characterized in terms of delay, energy, and endurance, using industrial EDA tools available at INL (e.g., Cadence Virtuoso/Spectre, Synopsys).In a second phase:- Ternary arithmetic operators (adders, multipliers) will be designed and evaluated for eCAT target applications, particularly convolutional neural networks.- Special attention will be given to introducing approximate computing through modulation of the ferroelectric programming scheme.- The resulting models will be abstracted at different levels and integrated into the project's system simulator to assess real-world gains in energy, precision, and performance.

Formation AcadémiqueMaster en microélectronique, génie électrique ou dans un domaine connexe.Compétences Techniques- Conception de circuits : Maîtrise des flots de conception numérique (schématique, simulation, synthèse) à l'aide d'outils EDA industriels, de préférence Cadence Virtuoso/Spectre et Synopsys.- Physique des composants : Solides connaissances en physique des dispositifs semiconducteurs et MOS ; une expérience préalable en mémoires non volatiles ou en matériaux ferroélectriques constitue un atout.- Logique numérique : Curiosité pour les paradigmes logiques non conventionnels tels que la logique multi-valuée et le calcul approximatif, ainsi que pour les nouvelles architectures mémoire.- Programmation et simulation : Maîtrise des langages de description matérielle (Verilog-A, VHDL ou Verilog) ; la programmation Python pour l'automatisation des simulations est un atout supplémentaire.Compétences Transversales- Rigueur scientifique et autonomie intellectuelle.- Capacité à travailler efficacement au sein d'un environnement collaboratif international, avec des interactions régulières avec les partenaires français et allemands du projet eCAT.LangueLa maîtrise de l'anglais scientifique (lecture, rédaction et présentation orale) est obligatoire.En résumé, le candidat idéal allie une solide formation en microélectronique et en physique des composants à une expérience pratique en conception de circuits, un intérêt marqué pour les paradigmes de calcul émergents, ainsi que les compétences en communication nécessaires pour s'épanouir dans un projet de recherche international.Application (CV including academic transcripts, cover letter) MUST be submitted through the following platform:https://ecolecentraledelyon.recruitee.com/o/centrale-lyon-doctorant-conception-de-circuit-ferroelectrique-pour-la-logique-ternaire/c/new?lang=en

• Python
• VHDL
• Langages de description et de programmation de matériel
• Anglais
• Autonomie
• Scheme
• Langage de description